Curated learning resources for GPU programming, MLIR, ML systems, inference optimization, and performance engineering. Each section is organized as its own learning track so compiler, kernel, and systems resources stay easy to scan.
CUDA / Triton / CuTe GPU Programming A structured path through GPU architecture, CUDA fundamentals, Triton, CUTLASS, CuTe DSL, GEMM, attention kernels, PTX, profiling, and modern ML systems performance work. CUDA Triton Performance
Compilers / IR / Lowering MLIR A segmented MLIR path covering official docs, hands-on tutorials, blogs, videos, compiler-stack case studies, papers, and research/social posts. Dialects Lowering IREE
GPU Programming
CUDA Foundations
Nick CUDA Crash Course Fast practical introduction to CUDA programming and kernel structure
Udacity Intro to Parallel Programming Classic foundations for parallel algorithms, CUDA kernels, scans, reductions, sorting, and GPU thinking
NVIDIA Modern CUDA C++ Programming Class Official NVIDIA CUDA training material covering modern CUDA C++ programming patterns
OLCF CUDA Training Series HPC-oriented CUDA lessons from Oak Ridge, useful for serious systems and performance practice
Cornell Virtual Workshop: CUDA Concepts Readable CUDA concept notes for kernels, grids, blocks, memory, and execution hierarchy
Triton, CuTe, CUTLASS, and DSLs
GEMM and Tensor Cores
How to Optimize a CUDA Matmul Kernel Canonical step-by-step CUDA SGEMM optimization path toward cuBLAS-like performance
Inside NVIDIA GPUs: High-Performance Matmul Kernels Architecture, PTX/SASS, warp tiling, asynchronous pipelines, and tensor-core matmul intuition
Modern GPU Matmul Optimization Register tiling, vectorized loads, shared-memory staging, cp.async, TMA, warp specialization, split-K, and tensor cores
Advanced Matrix Multiplication Optimization CUDA SGEMM optimization with inline PTX, asynchronous memory copies, double buffering, and bank-conflict avoidance
Tensor Cores for ML Systems Modern tensor-core programming concepts for ML workloads
Matrix Multiplication on Blackwell: Breaking SOTA Blackwell matmul optimization case study with cluster launch control and state-of-the-art performance targets
Attention and LLM Inference Kernels
PTX, SASS, and Hardware Internals
Deep Dives and Reference Collections
MLIR
Official Docs, Repos, and Reference Material
Tutorials and Hands-On Learning
Other Posts and Case Studies
From JAX to VLIW: Tracing a TPU Compiler Stack Post tracing JAX through HLO, MLIR, and TPU compiler codegen down toward VLIW execution
When XLA Is Not Enough: Pallas to VLIW Post on TPU compiler limits, algorithmic rewrites, Pallas, and low-level codegen realities
A TPU from Scratch: JAX to VLIW Case study connecting custom RTL, JAX, HLO, MLIR, assembly, VLIW, binary codegen, and PJRT backend work
MLIR Lowering Pipeline for Wafer-Scale Stencils Cerebras/EPCC post on MLIR lowering for stencil workloads on wafer-scale systems
GPU Compiler from Scratch Post about a browser-executable GPU compiler pipeline from source code to MLIR IR, register allocation, and binary instructions
Hexagon-MLIR Post on an AI compilation stack for Qualcomm neural processors and MLIR-based lowering
PolyBlocks Compiler Infrastructure Post on reusable compiler infrastructure for AI chips and PyTorch/JAX compilers for new accelerators